JPH0639463Y2 - 発光ダイオード素子の樹脂封止用リードフレーム - Google Patents

発光ダイオード素子の樹脂封止用リードフレーム

Info

Publication number
JPH0639463Y2
JPH0639463Y2 JP1987155339U JP15533987U JPH0639463Y2 JP H0639463 Y2 JPH0639463 Y2 JP H0639463Y2 JP 1987155339 U JP1987155339 U JP 1987155339U JP 15533987 U JP15533987 U JP 15533987U JP H0639463 Y2 JPH0639463 Y2 JP H0639463Y2
Authority
JP
Japan
Prior art keywords
resin
emitting diode
diode element
lead frame
resin material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1987155339U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0160559U (en]
Inventor
道男 長田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP1987155339U priority Critical patent/JPH0639463Y2/ja
Publication of JPH0160559U publication Critical patent/JPH0160559U/ja
Application granted granted Critical
Publication of JPH0639463Y2 publication Critical patent/JPH0639463Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP1987155339U 1987-10-09 1987-10-09 発光ダイオード素子の樹脂封止用リードフレーム Expired - Lifetime JPH0639463Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987155339U JPH0639463Y2 (ja) 1987-10-09 1987-10-09 発光ダイオード素子の樹脂封止用リードフレーム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987155339U JPH0639463Y2 (ja) 1987-10-09 1987-10-09 発光ダイオード素子の樹脂封止用リードフレーム

Publications (2)

Publication Number Publication Date
JPH0160559U JPH0160559U (en]) 1989-04-17
JPH0639463Y2 true JPH0639463Y2 (ja) 1994-10-12

Family

ID=31432879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987155339U Expired - Lifetime JPH0639463Y2 (ja) 1987-10-09 1987-10-09 発光ダイオード素子の樹脂封止用リードフレーム

Country Status (1)

Country Link
JP (1) JPH0639463Y2 (en])

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63287045A (ja) * 1987-05-19 1988-11-24 Sharp Corp 光半導体装置の製造方法

Also Published As

Publication number Publication date
JPH0160559U (en]) 1989-04-17

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